This application claims priority from Korean Application No. 2000-32392, filed on Jun. 13, 2000, in the name of Samsung Electronics Co., Ltd., and is incorporated herein by reference for all purposes.
1. Field of the Invention
The present invention relates to a method for forming a capacitor of a semiconductor memory device, and more particularly, to a method for forming a capacitor of a semiconductor memory device.
2. Description of the Related Art
A decrease in cell capacitance due to a reduction in memory cell areas makes it difficult to increase the integration density of semiconductor memory devices. Such decreased cell capacitance degrades the data readability from memory cells, increases a soft error rate, and also hinders the low-voltage operation of the semiconductor memory devices. Thus, the problem of decreased cell capacitance needs to be solved for ultra large-scale integrated, semiconductor memory devices.
To increase capacitance within a limited cell area, a method of thinning a dielectric layer of a capacitor or a method of forming a capacitor lower electrode with a cylindrical or pin-like structure so as to increase the effective area of a capacitor has been suggested. However, as for 1 gigabyte-or-more dynamic random access memories (DRAMs), with an existing dielectric layer formed of a nitride/oxide (NO) layer with bilayered structure, or a tantalum oxide layer, it is difficult to obtain a desired capacitance that is high enough to operate the memory device by the above suggested methods.
To solve this problem, research into use of a dielectric layer with a high dielectric constant, which is formed of, for example, (Ba,Sr)TiO3(BST), PbZrTiO3(PZT) and (Pb,La)(Zr,Ti)O3(PLZT), as a dielectric layer of a capacitor is being actively conducted.
For example, in fabricating a semiconductor memory device having a dielectric layer with a high dielectric constant, a lower electrode pad is formed of doped polysilicon in an impurity injection region of a semiconductor substrate. After forming a plug, which is electrically connected to a lower electrode pad, a capacitor lower electrode is formed on the plug. A dielectric layer with a high dielectric constant, or a ferroelectric layer is formed on the capacitor lower electrode as a capacitor dielectric layer, and then subjected to annealing at high temperatures in an oxygen atmosphere to crystalize the capacitor dielectric layer. As a result, the insulation characteristics of the capacitor dielectric layer is enhanced with increased capacitance and reduced leakage current of the capacitor. However, since the high-temperature annealing process is carried out at a temperature of 600-900xc2x0 C. under the oxygen atmosphere, if the capacitor lower electrode is formed of doped polysilicon, which is a well-known electrode material, then the capacitor lower electrode can oxidize during the high-temperature annealing process, thereby degrading contact resistance, or resulting in an unnecessary metal silicide layer between the capacitor dielectric layer and the capacitor lower electrode.
To avoid this problem, when a capacitor of a semiconductor memory device has a dielectric layer with a high dielectric constant, a platinum (Pt) group element, or an oxide of these elements, for example, Pt, iridium (Ir), ruthenium (Ru), ruthenium oxide (RuO2) or iridium oxide (IrO2), is typically used as an electrode material.
According to a conventional technique of forming a lower electrode with a Pt group element, a conductive layer is formed of a Pt group element and then patterned by dry etching to form the lower electrode. However, the dry etching method does not allow easy change of the Pt group element of the conductive layer into a gaseous form, and thus it is difficult to divide the lower electrode for individual cells. For example, when fabricating 4 gigabytes or more semiconductor memory devices having, in particular, a lower electrode with 300 nm or less width, the dry etching method has a limitation in forming the lower electrode. Thus, it would be desirable to provide a method suitable for forming a capacitor lower electrode, other than the dry etching method.
It is an objective of the present invention to provide a method for forming a capacitor of a semiconductor memory device by an electroplating method, rather than by a dry etching method.
To achieve the objective of the present invention, there is provided a method for forming a capacitor of a semiconductor memory device, comprising depositing a insulating layer over a semiconductor substrate, and patterning the insulating layer into a insulating pattern with a hole, which exposes the semiconductor substrate. The insulating pattern determines the dimension of a lower electrode.
Next, a seed layer is formed over the surface of the exposed semiconductor substrate, the inner walls of the hole, and the insulating pattern, and a plating mask layer is selectively formed on the seed layer deposited on the insulating pattern, and on a portion of the seed layer from the upper edges of the insulating pattern deposited along the sidewalls of the hole to a predetermined depth, such that the seed layer formed in the hole is exposed. The seed layer is formed of a conductive material to be used as an electrode for electroplating. The seed layer may be formed of a platinum group metal layer, a platinum group metal oxide layer, a conductive material layer with perovskite structure, a conductive metal layer, a metal silicide layer, a metal nitride layer, or a multi-layer of these layers. The plating mask layer may be formed of an insulating material such that it can be protected from deposition of a metal layer during electroplating. The plating mask layer may be selectively formed on the seed layer deposited on the insulating pattern, and on a portion of the seed layer from the upper edges of the insulating pattern deposited along the sidewalls of the hole to a predetermined depth, by a physical vapor deposition (PVD) or a plasma chemical vapor deposition (CVD) method, such that the seed layer formed in the hole can be exposed.
Next, a conductive layer is formed on the exposed seed layer by electroplating, filling the hole. When forming the conductive layer, a metal salt solution containing a Pt salt, Ir salt, Ru salt, Rh salt, Os salt, Pd salt, Au salt, Ag salt, Co salt, Ni salt or a composite salt of these metal salts can be used as a plating solution; Pt, Ir, Ru, Rh, Os, Pd, Au, Ag, Co, Ni or an alloy of these metals can be used as an anode; and the seed layer can be used as a cathode.
Next, the surfaces of the plating mask layer, the seed layer and the conductive layer are etched to be flat by, for example, a dry etching method or a chemical mechanical polishing (CMP) method, thereby forming a conductive pattern and a seed pattern separated by a unit cell. The insulating pattern formed on the outer walls of the hole is removed to complete a lower electrode of the capacitor formed of the conductive pattern. Then, a dielectric layer and an upper electrode are formed in succession on the lower electrode, thereby completing a capacitor.
In the formation of a capacitor of a semiconductor device according to the present invention, the conductive pattern to be a lower electrode can be formed just in a hole with a high aspect ratio by electroplating, without generation of a void in the hole, not by a dry etching method.